753 search results - page 32 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
111
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ACSD
2007
IEEE
15 years 7 months ago
2007
IEEE
Modern multiprocessor embedded systems execute a large number of tasks on shared processors and handle their complex communications on shared communication networks. Traditional m...
144
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IPPS
2005
IEEE
15 years 6 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
117
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MICAI
2005
Springer
15 years 6 months ago
2005
Springer
We propose a novel, high-level model of human learning and cognition, based on association forming. The model configures any input data stream featuring a high incidence of repeti...
114
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ESA
2004
Springer
15 years 6 months ago
2004
Springer
Our work is motivated by the problem of managing data on storage devices, typically a set of disks. Such storage servers are used as web servers or multimedia servers, for handling...
232
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FCCM
2011
IEEE
14 years 5 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...