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» Mechanisms for Mapping High-Level Parallel Performance Data
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HCW
2000
IEEE
15 years 5 months ago
Design of a Framework for Data-Intensive Wide-Area Applications
Applications that use collections of very large, distributed datasets have become an increasingly important part of science and engineering. With high performance wide-area networ...
Michael D. Beynon, Tahsin M. Kurç, Alan Sus...
IPPS
1999
IEEE
15 years 5 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ISPA
2007
Springer
15 years 7 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ICPP
1997
IEEE
15 years 5 months ago
Automatic Parallelization and Scheduling of Programs on Multiprocessors using CASCH
r The lack of a versatile software tool for parallel program development has been one of the major obstacles for exploiting the potential of high-performance architectures. In this...
Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu, Wei Shu
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 5 months ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park