Sciweavers

753 search results - page 50 / 151
» Mechanisms for Mapping High-Level Parallel Performance Data
Sort
View
CF
2006
ACM
15 years 5 months ago
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
Juan del Cuvillo, Weirong Zhu, Guang R. Gao
IPPS
1996
IEEE
15 years 5 months ago
Software Support for Virtual Memory-Mapped Communication
Virtual memory-mapped communication (VMMC) is a communication model providing direct data transfer between the sender's and receiver's virtual address spaces. This model...
Cezary Dubnicki, Liviu Iftode, Edward W. Felten, K...
88
Voted
CCGRID
2010
IEEE
15 years 2 months ago
A Map-Reduce System with an Alternate API for Multi-core Environments
Map-reduce framework has received a significant attention and is being used for programming both large-scale clusters and multi-core systems. While the high productivity aspect of ...
Wei Jiang, Vignesh T. Ravi, Gagan Agrawal
JSA
2007
162views more  JSA 2007»
15 years 1 months ago
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
CLOUD
2010
ACM
15 years 6 months ago
Making cloud intermediate data fault-tolerant
Parallel dataflow programs generate enormous amounts of distributed data that are short-lived, yet are critical for completion of the job and for good run-time performance. We ca...
Steven Y. Ko, Imranul Hoque, Brian Cho, Indranil G...