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» Mechanisms for Mapping High-Level Parallel Performance Data
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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 7 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
IPPS
2002
IEEE
15 years 6 months ago
Disconnected Operations in Mobile Environments
The execution of distributed applications involving mobile terminals and fixed servers connected by wireless links raises the need for handling network disconnections, both invol...
Denis Conan, Sophie Chabridon, Guy Bernard
ACL
2009
14 years 11 months ago
Data Cleaning for Word Alignment
Parallel corpora are made by human beings. However, as an MT system is an aggregation of state-of-the-art NLP technologies without any intervention of human beings, it is unavoida...
Tsuyoshi Okita
CCGRID
2006
IEEE
15 years 3 months ago
Integrating Logical and Physical File Models in the MPI-IO Implementation for "Clusterfile"
This paper presents the design and implementation of the MPI-IO interface for the Clusterfile parallel file system. The approach offers the opportunity of achieving a high corelat...
Florin Isaila, David E. Singh, Jesús Carret...
DOLAP
2010
ACM
14 years 11 months ago
Relational versus non-relational database systems for data warehousing
Relational database systems have been the dominating technology to manage and analyze large data warehouses. Moreover, the ER model, the standard in database design, has a close r...
Carlos Ordonez, Il-Yeol Song, Carlos Garcia-Alvara...