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» Mechanisms for store-wait-free multiprocessors
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CDES
2008
166views Hardware» more  CDES 2008»
15 years 1 months ago
Scalable Directory Organization for Tiled CMP Architectures
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
Alberto Ros, Manuel E. Acacio, José M. Garc...
JNW
2006
108views more  JNW 2006»
14 years 11 months ago
System-Level Fault Diagnosis Using Comparison Models: An Artificial-Immune-Systems-Based Approach
The design of large dependable multiprocessor systems requires quick and precise mechanisms for detecting the faulty nodes. The problem of system-level fault diagnosis is computati...
Mourad Elhadef, Shantanu Das, Amiya Nayak
IPPS
1998
IEEE
15 years 4 months ago
Efficient Runtime Thread Management for the Nano-Threads Programming Model
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
Dimitrios S. Nikolopoulos, Eleftherios D. Polychro...
PPOPP
1990
ACM
15 years 3 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
HPCA
2007
IEEE
15 years 6 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai