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» Mechanisms for store-wait-free multiprocessors
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ASPLOS
2006
ACM
15 years 5 months ago
SecCMP: a secure chip-multiprocessor architecture
Security has been considered as an important issue in processor design. Most of the existing mechanisms address security and integrity issues caused by untrusted main memory in si...
Li Yang, Lu Peng
CAMP
2005
IEEE
15 years 5 months ago
Bio-Inspired Computing Architectures: The Embryonics Approach
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
Gianluca Tempesti, Daniel Mange, André Stau...
ICPP
2005
IEEE
15 years 5 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
GECCO
2003
Springer
129views Optimization» more  GECCO 2003»
15 years 5 months ago
An Optimization Solution for Packet Scheduling: A Pipeline-Based Genetic Algorithm Accelerator
Abstract. The dense wavelength division multiplexing (DWDM) technique has been developed to provide a tremendous number of wavelengths/channels in an optical fiber. In the multi-c...
Shiann-Tsong Sheu, Yue-Ru Chuang, Yu-Hung Chen, Eu...
ICLP
2001
Springer
15 years 4 months ago
On a Tabling Engine That Can Exploit Or-Parallelism
Tabling is an implementation technique that improves the declarativeness and expressiveness of Prolog by reusing solutions to goals. Quite a few interesting applications of tabling...
Ricardo Rocha, Fernando M. A. Silva, Vítor ...