206 search results - page 37 / 42 » Mechanisms for store-wait-free multiprocessors |
TOMACS
1998
14 years 9 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
TPHOL
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...
CASES
2009
ACM
15 years 4 months ago
2009
ACM
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...