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CODES
2003
IEEE
15 years 8 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
112
Voted
EUROMICRO
2002
IEEE
15 years 8 months ago
A Sum of Absolute Differences Implementation in FPGA Hardware
In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
ISSTA
2009
ACM
15 years 8 months ago
Run-time conformance checking of mobile and distributed systems using executable models
This paper describes an approach for conformance testing of mobile and distributed systems. The approach is based on kiltera — a novel, high-level language supporting the descri...
Ahmad A. Saifan, Ernesto Posse, Jürgen Dingel
154
Voted
JSA
2002
130views more  JSA 2002»
15 years 3 months ago
Reconfigurable models of finite state machines and their implementation in FPGAs
This paper examines some models of FSMs that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a wa...
Valery Sklyarov
154
Voted
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
15 years 2 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...