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CODES
2003
IEEE
15 years 10 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
155
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ISORC
2003
IEEE
15 years 10 months ago
Probabilistic Simulation-Based Analysis of Complex Real-Time Systems
Many industrial real-time systems have evolved over a long period of time and were initially so simple that it was possible to predict consequences of adding new functionality by ...
Anders Wall, Johan Andersson, Christer Norströ...
ISPASS
2009
IEEE
15 years 11 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ESEM
2009
ACM
15 years 11 months ago
Using security metrics coupled with predictive modeling and simulation to assess security processes
: © Using Security Metrics Coupled with Predictive Modeling and Simulation to Assess Security Processes Yolanta Beres, Marco Casassa Mont, Jonathan Griffin, Simon Shiu HP Laborato...
Yolanta Beres, Marco Casassa Mont, Jonathan Griffi...
TASE
2011
IEEE
14 years 11 months ago
Multiclass Flow Line Models of Semiconductor Manufacturing Equipment for Fab-Level Simulation
—For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the cus...
James R. Morrison