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» Memory Access Schemes for Configurable Processors
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ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
15 years 1 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
HIPEAC
2011
Springer
13 years 9 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 1 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
ICPP
2003
IEEE
15 years 2 months ago
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
Xiaotong Zhuang, Hsien-Hsin S. Lee
ADBIS
1995
Springer
155views Database» more  ADBIS 1995»
15 years 1 months ago
The MaStA I/O Cost Model and its Validation Strategy
Crash recovery in database systems aims to provide an acceptable level of protection from failure at a given engineering cost. A large number of recovery mechanisms are known, and...
S. Scheuerl, Richard C. H. Connor, Ronald Morrison...