95 search results - page 3 / 19 » Memory Aware High-Level Synthesis for Embedded Systems |
DAC
2004
ACM
16 years 17 days ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
108
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SAMOS
2004
Springer
15 years 5 months ago
2004
Springer
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
112
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FPL
2009
Springer
15 years 3 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
80
Voted
FPL
2004
Springer
15 years 5 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
ASAP
2004
IEEE
15 years 3 months ago
2004
IEEE
As technology scales, transient faults have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability i...