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» Memory Bandwidth Limitations of Future Microprocessors
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HPCA
2007
IEEE
15 years 3 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
105
Voted
DEBS
2010
ACM
15 years 1 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
DANCE
2002
IEEE
15 years 2 months ago
Modeling CPU Demand in Heterogeneous Active Networks
Active-network technology envisions deploying execution environments in network elements so that application-specific processing can be applied to network traffic. To provide safe...
Virginie Galtier, Kevin L. Mills, Yannick Carlinet
FPL
2006
Springer
127views Hardware» more  FPL 2006»
15 years 1 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
ICPP
2005
IEEE
15 years 3 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...