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CC
2007
Springer
126views System Software» more  CC 2007»
15 years 4 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
15 years 2 months ago
Prefetching Using Markov Predictors
Prefetching is one approach to reducing the latency of memory operations in modern computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as an i...
Doug Joseph, Dirk Grunwald
DATE
2009
IEEE
117views Hardware» more  DATE 2009»
15 years 4 months ago
Using dynamic compilation for continuing execution under reduced memory availability
—This paper explores the use of dynamic compilation for continuing execution even if one or more of the memory banks used by an application become temporarily unavailable (but th...
Ozcan Ozturk, Mahmut T. Kandemir
DAC
2009
ACM
15 years 10 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
ISCA
2008
IEEE
92views Hardware» more  ISCA 2008»
15 years 4 months ago
Counting Dependence Predictors
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...
Franziska Roesner, Doug Burger, Stephen W. Keckler