Sciweavers

236 search results - page 43 / 48
» Memory Bank Predictors
Sort
View
HIPEAC
2011
Springer
13 years 12 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
102
Voted
IISWC
2006
IEEE
15 years 6 months ago
Performance Analysis of Sequence Alignment Applications
— Recent advances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a m...
Friman Sánchez, Esther Salamí, Alex ...
116
Voted
DIS
2006
Springer
15 years 2 months ago
Change Detection with Kalman Filter and CUSUM
Knowledge discovery systems are constrained by three main limited resources: time, memory and sample size. Sample size is traditionally the dominant limitation, but in many present...
Milton Severo, João Gama
PPOPP
2010
ACM
15 years 7 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 5 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...