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» Memory Capacity and Sentence Processing
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ICASSP
2011
IEEE
14 years 1 months ago
Hardware architectures for successive cancellation decoding of polar codes
The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancella...
Camille Leroux, Ido Tal, Alexander Vardy, Warren J...
CCGRID
2006
IEEE
15 years 3 months ago
The Computational and Storage Potential of Volunteer Computing
“Volunteer computing” uses Internet-connected computers, volunteered by their owners, as a source of computing power and storage. This paper studies the potential capacity of ...
David P. Anderson, Gilles Fedak
85
Voted
PATMOS
2005
Springer
15 years 3 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
ASAP
2003
IEEE
133views Hardware» more  ASAP 2003»
15 years 2 months ago
Storage Management in Process Networks using the Lexicographically Maximal Preimage
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...
Alexandru Turjan, Bart Kienhuis
SC
2009
ACM
15 years 4 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...