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ICS
1999
Tsinghua U.
15 years 6 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
ICML
2005
IEEE
16 years 2 months ago
Combining model-based and instance-based learning for first order regression
T ORDER REGRESSION (EXTENDED ABSTRACT) Kurt Driessensa Saso Dzeroskib a Department of Computer Science, University of Waikato, Hamilton, New Zealand (kurtd@waikato.ac.nz) b Departm...
Kurt Driessens, Saso Dzeroski
AROBOTS
2008
158views more  AROBOTS 2008»
15 years 2 months ago
Learning traversability models for autonomous mobile vehicles
Autonomous mobile robots need to adapt their behavior to the terrain over which they drive, and to predict the traversability of the terrain so that they can effectively plan thei...
Michael Shneier, Tommy Chang, Tsai Hong, William P...
NIPS
2000
15 years 3 months ago
Learning Winner-take-all Competition Between Groups of Neurons in Lateral Inhibitory Networks
It has long been known that lateral inhibition in neural networks can lead to a winner-take-all competition, so that only a single neuron is active at a steady state. Here we show...
Xiaohui Xie, Richard H. R. Hahnloser, H. Sebastian...
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
15 years 8 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang