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» Memory Dependence Prediction Using Store Sets
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ACMMSP
2004
ACM
131views Hardware» more  ACMMSP 2004»
15 years 7 months ago
Reuse-distance-based miss-rate prediction on a per instruction basis
Feedback-directed optimization has become an increasingly important tool in designing and building optimizing compilers. Recently, reuse-distance analysis has shown much promise i...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
IPSN
2007
Springer
15 years 8 months ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava
RTAS
1997
IEEE
15 years 6 months ago
OS-Controlled Cache Predictability for Real-Time Systems
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
Jochen Liedtke, Hermann Härtig, Michael Hohmu...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
15 years 8 months ago
Operating System Controlled Processor-Memory Bus Encryption
—Unencrypted data appearing on the processor– memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Al...
Xi Chen, Robert P. Dick, Alok N. Choudhary
PVLDB
2008
96views more  PVLDB 2008»
15 years 1 months ago
H-store: a high-performance, distributed main memory transaction processing system
Our previous work has shown that architectural and application shifts have resulted in modern OLTP databases increasingly falling short of optimal performance [10]. In particular,...
Robert Kallman, Hideaki Kimura, Jonathan Natkins, ...