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» Memory Design for Constrained Dynamic Optimization Problems
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105
Voted
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 9 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
98
Voted
ARCS
2006
Springer
15 years 6 months ago
Dynamic Dictionary-Based Data Compression for Level-1 Caches
Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
Georgios Keramidas, Konstantinos Aisopos, Stefanos...
165
Voted
RTAS
2010
IEEE
15 years 14 days ago
Using PCM in Next-generation Embedded Space Applications
Abstract--Dynamic RAM (DRAM) has been the best technology for main memory for over thirty years. In embedded space applications, radiation hardened DRAM is needed because gamma ray...
Alexandre Peixoto Ferreira, Bruce R. Childers, Ram...
USENIX
1996
15 years 3 months ago
Transparent Fault Tolerance for Parallel Applications on Networks of Workstations
This paper describes a new method for providingtransparent fault tolerance for parallel applications on a network of workstations. We have designed our method in the context of sh...
Daniel J. Scales, Monica S. Lam
116
Voted
KESAMSTA
2010
Springer
15 years 4 months ago
Modelling Dynamic Forgetting in Distributed Information Systems
Abstract. We describe and model a new aspect in the design of distributed information systems. We build upon a previously described problem on the microlevel, which asks how quickl...
Nicolas Höning, Martijn C. Schut