1184 search results - page 164 / 237 » Memory Design for Constrained Dynamic Optimization Problems |
109
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ICS
2009
Tsinghua U.
15 years 8 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
135
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FPGA
2007
ACM
15 years 8 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
136
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LCTRTS
2007
Springer
15 years 8 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
165
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PLDI
2003
ACM
15 years 7 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
130
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DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
—We present an optimal methodology for dynamic voltage scheduling problem in the presence of realistic assumption such as leakage-power and intra-task overheads. Our contribution...