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» Memory Design for Constrained Dynamic Optimization Problems
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LCTRTS
2010
Springer
14 years 7 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
INFOCOM
2011
IEEE
14 years 1 months ago
Space-time tradeoff in regular expression matching with semi-deterministic finite automata
Abstract—Regular expression matching (REM) with nondeterministic finite automata (NFA) can be computationally expensive when a large number of patterns are matched concurrently....
Yi-Hua E. Yang, Viktor K. Prasanna
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 6 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
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VRML
2004
ACM
15 years 2 months ago
PathSim visualizer: an Information-Rich Virtual Environment framework for systems biology
Increasingly, biology researchers and medical practitioners are using computational tools to model and analyze dynamic systems across scales from the macro to the cellular to the ...
Nicholas F. Polys, Doug A. Bowman, Chris North, Re...
INFOCOM
2009
IEEE
15 years 4 months ago
An Economically-Principled Generative Model of AS Graph Connectivity
We explore the problem of modeling Internet connectivity at the Autonomous System (AS) level and present an economically-principled dynamic model that reproduces key features of t...
Jacomo Corbo, Shaili Jain, Michael Mitzenmacher, D...