1184 search results - page 73 / 237 » Memory Design for Constrained Dynamic Optimization Problems |
106
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FMCAD
2009
Springer
15 years 9 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
108
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WMPI
2004
ACM
15 years 7 months ago
2004
ACM
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
110
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ECCV
1996
Springer
16 years 4 months ago
1996
Springer
An approach is presented for imposing generic hard constraints on deformable models at a low computational cost, while preserving the good convergence properties of snake-like mod...
116
Voted
ASPDAC
2004
ACM
15 years 7 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
135
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RAS
2007
15 years 1 months ago
2007
This paper addresses the problem of vision-based navigation and proposes an original control law to perform such navigation. The overall approach is based on an appearance-based r...