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» Memory Exploration for Low Power, Embedded Systems
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SEUS
2009
IEEE
15 years 11 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...
RTAS
2005
IEEE
15 years 10 months ago
Practical On-line DVS Scheduling for Fixed-Priority Real-Time Systems
We present an on-line Dynamic Voltage Scaling (DVS) algorithm for preemptive fixed-priority real-time systems called low power Limited Demand Analysis with Transition overhead (l...
Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
154
Voted
IPPS
2002
IEEE
15 years 9 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
116
Voted
ERSA
2006
70views Hardware» more  ERSA 2006»
15 years 6 months ago
Differential Reconfiguration Architecture suitable for a Holographic Memory
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobaya...
ASPDAC
2001
ACM
83views Hardware» more  ASPDAC 2001»
15 years 8 months ago
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
Tony Givargis, Frank Vahid, Jörg Henkel