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» Memory System Connectivity Exploration
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88
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HIPC
2005
Springer
15 years 9 months ago
The Potential of On-Chip Multiprocessing for QCD Machines
We explore the opportunities offered by current and forthcoming VLSI technologies to on-chip multiprocessing for Quantum Chromo Dynamics (QCD), a computational grand challenge for ...
Gianfranco Bilardi, Andrea Pietracaprina, Geppino ...
ICFP
2006
ACM
16 years 3 months ago
The development of Chez Scheme
Chez Scheme is now over 20 years old, the first version having been released in 1985. This paper takes a brief look back on the history of Chez Scheme's development to explor...
R. Kent Dybvig
ICC
2007
IEEE
15 years 9 months ago
Computing Maximum-Likelihood Bounds for Reed-Solomon Codes over Partial Response Channels
Abstract—Computing maximum-likelihood bounds on the performance of systems involving partial response (PR) channels, with or without an error correcting code present, is rather c...
Richard M. Todd, J. R. Cruz
106
Voted
IJCNN
2006
IEEE
15 years 9 months ago
SOM-Based Sparse Binary Encoding for AURA Classifier
—The AURA k-Nearest Neighbour classifier associates binary input and output vectors, forming a compact binary Correlation Matrix Memory (CMM). For a new input vector, matching ve...
Simon O'Keefe
129
Voted
SAMOS
2005
Springer
15 years 8 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He