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HPCA
2007
IEEE
15 years 9 months ago
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Albert Meixner, Daniel J. Sorin
ICPPW
2002
IEEE
15 years 8 months ago
Experiments with Parallelizing a Tribology Application
Different parallelization methods vary in their system requirements, programming styles, efficiency of exploring parallelism, and the application characteristics they can handle....
Vipin Chaudhary, W. L. Hase, Hai Jiang, L. Sun, Da...
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
15 years 7 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
15 years 8 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
ICAC
2005
IEEE
15 years 8 months ago
The Case for Automated Planning in Autonomic Computing
Computing systems have become so complex that the IT industry recognizes the necessity of deliberative methods to make these systems self-configuring, self-healing, selfoptimizin...
Biplav Srivastava, Subbarao Kambhampati