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CODES
2004
IEEE
15 years 3 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 3 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
SEUS
2009
IEEE
15 years 6 months ago
A Single-Path Chip-Multiprocessor System
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...
Martin Schoeberl, Peter P. Puschner, Raimund Kirne...
DAC
2009
ACM
16 years 19 days ago
PDRAM:a hybrid PRAM and DRAM main memory system
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges in...
Gaurav Dhiman, Raid Ayoub, Tajana Rosing
DAC
2009
ACM
15 years 6 months ago
PDRAM: a hybrid PRAM and DRAM main memory system
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
Gaurav Dhiman, Raid Ayoub, Tajana Rosing