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DAC
2009
ACM
16 years 5 months ago
An SDRAM-aware router for Networks-on-Chip
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
Wooyoung Jang, David Z. Pan
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
15 years 4 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
145
Voted
DATE
2005
IEEE
138views Hardware» more  DATE 2005»
15 years 6 months ago
BB-GC: Basic-Block Level Garbage Collection
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze la...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
IEEEPACT
2006
IEEE
15 years 10 months ago
Compiling for stream processing
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abhishek Das, William J. Dally, Peter R. Mattson
LCN
2007
IEEE
15 years 10 months ago
A Distributed Scheduling Approach for Ethernet-based Passive Optical Networks
— Ethernet-based Passive Optical Networks (EPON) are being considered as the best candidates for the next generation broadband access networks. Several algorithms for dynamic ban...
Marilet De Andrade, Lluís Gutierrez, Sebast...