3202 search results - page 131 / 641 » Memory access scheduling |
115
Voted
ICCD
2005
IEEE
16 years 1 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
146
Voted
TCSV
2002
15 years 4 months ago
2002
Abstract--In this paper, we propose a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the ...
121
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ICC
2007
IEEE
15 years 11 months ago
2007
IEEE
1 Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
133
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DAM
2007
15 years 4 months ago
2007
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to ...
147
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MIDDLEWARE
2010
Springer
15 years 3 months ago
2010
Springer
Abstract. Developing efficient distributed applications while managing complexity can be challenging. Managing network latency is a key challenge for distributed applications. We ...