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HPCA
2001
IEEE
16 years 5 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
186
Voted
MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
15 years 8 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
ASPDAC
2001
ACM
117views Hardware» more  ASPDAC 2001»
15 years 8 months ago
Low power techniques for address encoding and memory allocation
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
Wei-Chung Cheng, Massoud Pedram
CN
2004
86views more  CN 2004»
15 years 4 months ago
Management of abusive and unfair Internet access by quota-based priority control
In a free of charge or flat-rate Internet access environment, there often exists abusive and unfair usage of network resources. In this paper, the Internet access by the dormitory...
Tsung-Ching Lin, Yeali S. Sun, Shi-Chung Chang, Sh...
176
Voted
WIOPT
2010
IEEE
15 years 2 months ago
Optimal slotted random access in coded wireless packet networks
Abstract—We consider the problem of jointly optimizing random access and subgraph selection in coded wireless packet networks. As opposed to the corresponding scheduling approach...
Maximilian Riemensberger, Michael Heindlmaier, And...