Sciweavers

3202 search results - page 153 / 641
» Memory access scheduling
Sort
View
FCCM
2005
IEEE
107views VLSI» more  FCCM 2005»
15 years 10 months ago
Hardware Solution to Java Compressed Heap
Java technology has been integrated into mobile/wireless computing because of its rich support to portability (crossplatform nature), reusability (development libraries), and shor...
Mayumi Kato, Chia-Tien Dan Lo
ICS
1992
Tsinghua U.
15 years 9 months ago
Optimizing for parallelism and data locality
Previous research has used program transformation to introduce parallelism and to exploit data locality. Unfortunately,these twoobjectives have usuallybeen considered independentl...
Ken Kennedy, Kathryn S. McKinley
ASAP
2007
IEEE
116views Hardware» more  ASAP 2007»
15 years 6 months ago
The Design of a Novel Object-oriented Processor : OOMIPS
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
Weixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran
MOBICOM
2004
ACM
15 years 10 months ago
Exploiting medium access diversity in rate adaptive wireless LANs
Recent years have seen the growing popularity of multi-rate wireless network devices (e.g., 802.11a cards) that can exploit variations in channel conditions and improve overall ne...
Zhengrong Ji, Yi Yang, Junlan Zhou, Mineo Takai, R...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 10 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...