3202 search results - page 164 / 641 » Memory access scheduling |
123
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ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
154
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HPCA
1999
IEEE
15 years 9 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
156
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ICCD
1999
IEEE
15 years 9 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
157
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LCTRTS
2000
Springer
15 years 8 months ago
2000
Springer
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
158
Voted
ARVLSI
1997
IEEE
15 years 8 months ago
1997
IEEE
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...