3202 search results - page 16 / 641 » Memory access scheduling |
165
Voted
IPPS
2010
IEEE
15 years 1 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
130
Voted
IWOMP
2009
Springer
15 years 8 months ago
2009
Springer
Abstract. Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-...
127
Voted
MICRO
2005
IEEE
15 years 9 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
137
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
134
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...