3202 search results - page 170 / 641 » Memory access scheduling |
120
Voted
ACIVS
2008
Springer
15 years 7 months ago
2008
Springer
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
140
Voted
ICIP
2000
IEEE
16 years 6 months ago
2000
IEEE
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
134
click to vote
ICON
2007
IEEE
15 years 11 months ago
2007
IEEE
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...
139
click to vote
CCECE
2006
IEEE
15 years 11 months ago
2006
IEEE
— Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper ...
139
click to vote
VLDB
1992
ACM
15 years 9 months ago
1992
ACM
This paper presents a portable, efficient method for accessing memory resident persistent objects in virtual memory in the context of the E programming language. Under the approac...