3202 search results - page 201 / 641 » Memory access scheduling |
156
click to vote
MVA
1992
15 years 7 months ago
1992
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
158
Voted
ICPP
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper we work on the parallelization of the inherently serial Dijkstra's algorithm on modern multicore platforms. Dijkstra's algorithm is a greedy algorithm that ...
261
click to vote
GIS
2003
ACM
16 years 7 months ago
2003
ACM
For many applications with spatial data management such as Geographic Information Systems (GIS), block-oriented access over flash memory could introduce a significant number of no...
158
click to vote
ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
151
click to vote
ISCA
2007
IEEE
16 years 10 days ago
2007
IEEE
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...