3202 search results - page 233 / 641 » Memory access scheduling |
150
Voted
PPOPP
2009
ACM
16 years 6 months ago
2009
ACM
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of ...
154
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HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
147
Voted
HPCA
2001
IEEE
16 years 6 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
159
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TACAS
2010
Springer
16 years 1 months ago
2010
Springer
Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratchpad” memories. The price for increase...
143
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DATE
2009
IEEE
16 years 29 days ago
2009
IEEE
NAND Flash Memories require Garbage Collection (GC) and Wear Leveling (WL) operations to be carried out by Flash Translation Layers (FTLs) that oversee flash management. Owing to ...