3202 search results - page 238 / 641 » Memory access scheduling |
152
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PODC
2005
ACM
15 years 12 months ago
2005
ACM
The obstruction-free Dynamic Software Transactional Memory (DSTM) system of Herlihy et al. allows only one transaction at a time to acquire an object for writing. Should a second ...
189
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WMPI
2004
ACM
15 years 11 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
167
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ICPP
2002
IEEE
15 years 11 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
153
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ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata inform...
159
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OSDI
1994
ACM
15 years 7 months ago
1994
ACM
Traditional operating systems use a xed LRU-like page replacement policy and centralized frame pool that cannot properly serve all types of memory access patterns of various appli...