3202 search results - page 35 / 641 » Memory access scheduling |
101
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
110
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HICSS
1995
IEEE
15 years 5 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
115
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FPL
2000
Springer
15 years 5 months ago
2000
Springer
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...
109
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CODES
2000
IEEE
15 years 6 months ago
2000
IEEE
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
CGO
2003
IEEE
15 years 6 months ago
2003
IEEE
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...