3202 search results - page 83 / 641 » Memory access scheduling |
SIGCSE
1999
ACM
15 years 8 months ago
1999
ACM
In this paper, we presenttwo packagesthat simulate the multilevel feedbackqueueschedulingalgorithm for a single CPU,andfive pagereplacementalgorithmsthat areusedin the context of ...
121
Voted
ISCA
1998
IEEE
15 years 8 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
149
Voted
CORR
2011
Springer
14 years 10 months ago
2011
Springer
—We present a new model for distributed shared memory systems, based on remote data accesses. Such features are offered by network interface cards that allow one-sided operations...
119
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
134
Voted
ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...