3202 search results - page 93 / 641 » Memory access scheduling |
132
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HIPC
2005
Springer
15 years 10 months ago
2005
Springer
We examine the problem of scheduling concurrent independent flows on multiple-disk I/O storage systems. Two models are considered: in the shared buffer model the memory buffer is ...
138
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
127
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
152
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IEEEPACT
2003
IEEE
15 years 9 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
127
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ICPP
2003
IEEE
15 years 9 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...