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» Memory and compiler optimizations for low-power and -energy
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CASES
2005
ACM
15 years 3 days ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
15 years 3 months ago
Compiling for instruction cache performance on a multithreaded architecture
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
Rakesh Kumar, Dean M. Tullsen
BIRTHDAY
2009
Springer
15 years 2 months ago
Pervasive Theory of Memory
For many aspects of memory theoretical treatment already exists, in particular for: simple cache construction, store buers and store buer forwarding, cache coherence protocols, o...
Ulan Degenbaev, Wolfgang J. Paul, Norbert Schirmer
HPCN
1994
Springer
15 years 2 months ago
Experiments with HPF Compilation for a Network of Workstations
Abstract. High Performance Fortran (hpf) is a data-parallel Fortran for Distributed Memory Multiprocessors. Hpf provides an interesting programming model but compilers are yet to c...
Fabien Coelho
ISHPC
2000
Springer
15 years 1 months ago
Implementation and Evaluation of OpenMP for Hitachi SR8000
This paper describes the implementation and evaluation of the OpenMP compiler designed for the Hitachi SR8000 Super Technical Server. The compiler performs parallelization for the ...
Yasunori Nishitani, Kiyoshi Negishi, Hiroshi Ohta,...