354 search results - page 23 / 71 » Memory and compiler optimizations for low-power and -energy |
99
Voted
FCCM
2005
IEEE
15 years 3 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
98
Voted
EMSOFT
2010
Springer
14 years 8 months ago
2010
Springer
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
91
Voted
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ACMMSP
2004
ACM
15 years 3 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
105
Voted
ISPDC
2010
IEEE
14 years 8 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...