354 search results - page 51 / 71 » Memory and compiler optimizations for low-power and -energy |
86
Voted
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
117
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EUROPAR
2010
Springer
14 years 11 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
85
Voted
ICS
2007
Tsinghua U.
15 years 4 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
82
Voted
LCPC
2009
Springer
15 years 2 months ago
2009
Springer
The advent of multicores presents a promising opportunity for exploiting fine grained parallelism present in programs. Programs parallelized in the above fashion, typically involv...
78
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OOPSLA
2004
Springer
15 years 3 months ago
2004
Springer
This paper introduces dynamic object colocation, an optimization to reduce copying costs in generational and other incremental garbage collectors by allocating connected objects t...