354 search results - page 52 / 71 » Memory and compiler optimizations for low-power and -energy |
112
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HIPC
1999
Springer
15 years 6 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
110
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IWMM
2007
Springer
15 years 8 months ago
2007
Springer
Numerous optimizations exist for improving the performance of nondeferred reference-counting (RC) garbage collection. Their designs are ad hoc, intended to exploit different count...
134
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
ICCD
2003
IEEE
15 years 11 months ago
2003
IEEE
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits suf...
108
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CC
2001
Springer
15 years 6 months ago
2001
Springer
We study the application of a standard model checker tool, Spin, to the well-known problem of computing a may-alias relation for a C program. A precise may-alias relation can signi...