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» Memory and compiler optimizations for low-power and -energy
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CC
2009
Springer
106views System Software» more  CC 2009»
15 years 5 months ago
Blind Optimization for Exploiting Hardware Features
Software systems typically exploit only a small fraction of the realizable performance from the underlying microprocessors. While there has been much work on hardware-aware optimiz...
Dan Knights, Todd Mytkowicz, Peter F. Sweeney, Mic...
100
Voted
LCTRTS
2009
Springer
15 years 5 months ago
Live-range unsplitting for faster optimal coalescing
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...
Sandrine Blazy, Benoît Robillard
83
Voted
LCPC
2005
Springer
15 years 3 months ago
Scalable Array SSA and Array Data Flow Analysis
Static Single Assignment (SSA) has been widely accepted as the intermediate program representation of choice in most modern compilers. It allows for a much more efficient data flo...
Silvius Rus, Guobin He, Lawrence Rauchwerger
93
Voted
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 4 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
PLDI
2010
ACM
15 years 3 months ago
Decoupled lifeguards: enabling path optimizations for dynamic correctness checking tools
Dynamic correctness checking tools (a.k.a. lifeguards) can detect a wide array of correctness issues, such as memory, security, and concurrency misbehavior, in unmodified executa...
Olatunji Ruwase, Shimin Chen, Phillip B. Gibbons, ...