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» Memory and compiler optimizations for low-power and -energy
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116
Voted
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CGO
2005
IEEE
15 years 3 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
APLAS
2005
ACM
15 years 3 months ago
Transformation to Dynamic Single Assignment Using a Simple Data Flow Analysis
This paper presents a novel method to construct a dynamic single assignment (DSA) form of array-intensive, pointer-free C programs (or in any other procedural language). A program ...
Peter Vanbroekhoven, Gerda Janssens, Maurice Bruyn...
122
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VEE
2006
ACM
150views Virtualization» more  VEE 2006»
15 years 4 months ago
Evaluating fragment construction policies for SDT systems
Software Dynamic Translation (SDT) systems have been used for program instrumentation, dynamic optimization, security policy enforcement, intrusion detection, and many other uses....
Jason Hiser, Daniel Williams, Adrian Filipi, Jack ...
IPPS
2005
IEEE
15 years 3 months ago
Automatic Support for Irregular Computations in a High-Level Language
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
Jimmy Su, Katherine A. Yelick