Sciweavers

110 search results - page 3 / 22
» Memory hierarchy exploration for low power architectures in ...
Sort
View
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
13 years 11 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 10 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 15 days ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 10 months ago
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
In data dominated applications, like multi-media and telecom applications, data storage and transfers are the most important factors in terms of energy consumption, area and syste...
Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytac...
DAC
2001
ACM
14 years 7 months ago
Coupling-Driven Bus Design for Low-Power Application-Specific Systems
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
Youngsoo Shin, Takayasu Sakurai