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» Memory modeling for system synthesis
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138
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SIGSOFT
2009
ACM
16 years 6 months ago
Synthesizing partial component-level behavior models from system specifications
Initial system specifications, such as use-case scenarios and properties, only partially specify the future system. We posit that synthesizing partial component-level behavior mod...
Ivo Krka, Yuriy Brun, George Edwards, Nenad Medvid...
168
Voted
AUTOMATICA
2007
104views more  AUTOMATICA 2007»
15 years 6 months ago
Improving off-line approach to robust MPC based-on nominal performance cost
This paper gives two alternative off-line synthesis approaches to robust model predictive control (RMPC) for systems with polytopic description. In each approach, a sequence of ex...
BaoCang Ding, YuGeng Xi, Marcin T. Cychowski, Thom...
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
15 years 10 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
160
Voted
ISORC
2009
IEEE
16 years 15 days ago
Thread-Local Scope Caching for Real-time Java
There is increasing convergence between the fields of parallel and embedded computing. The demand for more functionality in embedded devices means that complex multicore architec...
Andy J. Wellings, Martin Schoeberl
CODES
2006
IEEE
15 years 12 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...