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» Memory modeling for system synthesis
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IPPS
2003
IEEE
15 years 11 months ago
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Dennis Abts, Steve Scott, David J. Lilja
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
15 years 9 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
15 years 10 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
NECO
1998
100views more  NECO 1998»
15 years 5 months ago
Memory Maintenance via Neuronal Regulation
Since their conception half a century ago Hebbian cell assemblies have become a basic term in the Neurosciences, and the idea that learning takes place through synaptic modi catio...
David Horn, Nir Levy, Eytan Ruppin
IEEEPACT
2006
IEEE
15 years 12 months ago
Testing implementations of transactional memory
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi...