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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
14 years 9 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
MASCOTS
2010
15 years 1 months ago
Modeling the Run-time Behavior of Transactional Memory
In this paper, we develop a queuing theory based analytical model to evaluate the performance of transactional memory. Based on the statistical characteristics observed on actual e...
Zhengyu He, Bo Hong
CGO
2009
IEEE
15 years 6 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
Michael F. Spear, Maged M. Michael, Michael L. Sco...
CODES
2005
IEEE
15 years 5 months ago
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer man...
Hyunok Oh, Nikil D. Dutt, Soonhoi Ha
CC
2007
Springer
15 years 3 months ago
Program Refactoring, Program Synthesis, and Model-Driven Development
Program refactoring, feature-based and aspect-oriented software synthesis, and model-driven development are disjoint research areas. However, they are all architectural metaprogram...
Don S. Batory