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RTAS
2006
IEEE
15 years 3 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
PPOPP
2003
ACM
15 years 3 months ago
Improving server software support for simultaneous multithreaded processors
Simultaneous multithreading (SMT) represents a fundamental shift in processor capability. SMT's ability to execute multiple threads simultaneously within a single CPU offers ...
Luke McDowell, Susan J. Eggers, Steven D. Gribble
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 2 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
ECAI
1994
Springer
15 years 1 months ago
The DUAL Cognitive Architecture: A Hybrid Multi-Agent Approach
1 A hybrid (symbolic/connectionist) cognitive architecture, DUAL, is proposed. It is a multi-agent system which consist of a large number of non-cognitive, relatively simple agents...
Boicho N. Kokinov
ASPLOS
2006
ACM
15 years 1 months ago
Integrated network interfaces for high-bandwidth TCP/IP
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kerne...
Nathan L. Binkert, Ali G. Saidi, Steven K. Reinhar...