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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 2 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
CORR
2006
Springer
116views Education» more  CORR 2006»
13 years 6 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...
ISSS
2000
IEEE
128views Hardware» more  ISSS 2000»
13 years 10 months ago
Hardware Synthesis from SPDF Representation for Multimedia Applications
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Chanik Park, Soonhoi Ha
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
13 years 10 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
LATIN
2004
Springer
13 years 11 months ago
Distributed Games and Distributed Control for Asynchronous Systems
Abstract. We introduce distributed games over asynchronous transition systems to model a distributed controller synthesis problem. A game involves two teams and is not turn-based: ...
Paul Gastin, Benjamin Lerman, Marc Zeitoun